The present disclosure relates to semiconductor device fabrication, and more specifically, to methods of reducing fin width, for example to mitigate low voltage strap bit fails.
With increasing miniaturization of electronics, non-planar fin-shaped field effect transistors (FinFETs) are increasingly incorporated into devices such as static random access memory (SRAM) bitcell arrays, logic devices, etc. Towards the end of semiconductor device formation, e.g. SRAM bitcell formation, termination boundaries of an array of such devices may be established, for example in the bit-line (BL) direction and in the wordline (WL) direction. Conventional termination techniques, such as “strap” design, are designed to preserve bitcell layout consistency and homogeneity in the electrical characteristics of the bitcells of the devices. One result of conventional array termination includes a systematic device offset, e.g. systematic strap proximity effect (SPE), which includes increased read currents in bitcells near the strap, decreased cell stability, decreased pull down (PD) and/or pass gate (PG) threshold voltage (VT), and increased low voltage fail count for adjacent strap region bitcells.